Gil Has Never Grasped the Nature of a Simulation Model
| September 30, 2006 | Posted by GilDodgen under Intelligent Design |
Tom English challenged me with this:
I say categorically, as someone who has worked in evolutionary computation for 15 years, that Gil does not understand what he is talking about. This is not to say that he is trying to mislead anyone. It is simply clear that he has never grasped the nature of a simulation model. His comments reflect the sort of concrete thinking I have tried to help many students grow beyond, often without success.
The reason for Tom’s lack of success is that he, and Darwinists in general, try to explain everything with an overly — indeed catastrophically — simplistic model. Here’s what’s involved in a real-world computer simulation:
My mathematical, computational, and engineering specialty is guided-airdrop technology. The results of my computer simulations, and their integration into the mechanics of smart parachutes, are now being used to resupply U.S. forces in Afghanistan. C-130 and C-17 aircraft can now drop payloads from up to 25,000 feet MSL, out of range of enemy small-arms, shoulder-launched missile, and RPG fire, and the payloads autonomously guide themselves to their targets within a CEP (circular error probable) of approximately 26 meters. Did I do all of this highly sophisticated mathematical and software simulation without ever having “grasped the nature of a simulation model”?
One small part of developing this technology involves mathematically and computationally simulating the descent rate of a parachute and its payload at various altitudes. This includes the following: the drag coefficient of the parachute, the chute reference area, the density of the air at various altitudes (not only determined by altitude but lapse rate — the rate at which air temperature changes with altitude), and other subtle considerations, such as the flow-field effects of the payload which changes the drag characteristics of the parachute.
If any mathematical, computational, or real-world assumptions about any of these factors are wrong, or if any unforeseen factors are left out (and what I described above represents a small percentage of what’s involved), the simulation breaks down. We do our best, but we never know for sure until we throw the thing out of an airplane, see where it lands, and tediously analyze the telemetry data recorded by the in-flight computer.
Based on these observations and computer simulations that can be tested in the real world, what confidence can anyone have that biological evolutionary computer simulations have anything to do with reality?
The answer is: none. It’s all fantasy and speculation, masquerading as science.
200 Responses to Gil Has Never Grasped the Nature of a Simulation Model
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DS said:
“Both Behe and Dembski have conceded that exaptation may produce what otherwise appears to be irreducible complexity.”
I want to parse what you are saying correctly in the context of this exchange. So what follows is a real (not rhetorical) question:
Is it correct to express their concession as, “We concede that stepwise processes (exaptation, scaffolding, etc.) can create structures that are indistinguishable from true IC structures, when evaluated in terms of the Behe/Demski definitions quoted above. However, these structures are not, by definition, truly IC because they were created by stepwise processes.”
Is that correct?
PaV said:
“I hope my response to you points out to you the lack of logic in Karl’s assertion. Only in a completely “abstract†way is such a statement correct.”
Well, you dismiss the “abstract,” logical structure of such assertions at your peril. The hazard is that you will come away with a meaning other than was intended by the speaker. As I read it, and again IMBDO, you’ve parsed (great word) Karl’s statement incorrectly and attributed to him an assertion that I don’t read him as having made, at least not in the exchange to which I was referring.
But, why thrash it further?
Dr. JAD:
I didn’t believe that anyone could still be so weak minded as to imagine that the production of dog varieties ever had anything to do with creative evolution, but here we have David vun Kannon claiming exactly that.
Er, no. What I said was that Darwin, himself, used artificial selection as an example of a process.
PaV:
“I now understand how this particular thread got started, and why Gil started it with the example he did.”
It started with the thread entitled “A Realistic Computational Simulation of Random Mutation Filtered by Natural Selection in Biology.” If you haven’t read that, you’ve started in the middle.
“my suspicion is that when the first models don’t produce this IC, that some tweaking takes place…. ”
Just so we are clear: You just made all that up.
recip
No, that’s putting words in their mouths. What I said requires no parsing into other words.
Recip B -
That isn’t correct. The ‘irreducable’ part of IC is the key. They concede complexity can arise step-wise. When one encounters a complex system which will not function without interacting essential components, one encounters something that cannot be reduced and still retain function.
A wind up clock is an example. Core gears work in unison, driven by a loaded spring. Pop open a wound clock a and start removing parts and see how long it keeps time. For this type of clock to work the core components must be assembled at the same time. Once assembled it is irreducably complex.
And that’s just the base consideration – as it applies to biology, one also has to factor how the complex structure fits into the overall scheme. Consider how ATP in required for cellular life and is produced in a complex machine – where is the step-wise explanation/demonstration of how cells lived while this complex assembly was gradually arising, being ‘selected’ by natural forces? Does ‘Science’ fully understand the genetic blueprints for this assembly? Which parts of the DNA code for the proteins needed for ATP synthase? Do we even know
Dang, I wish you guys let us edit our posts like Mike Gene does….
Recip, the above refers to #181
PaV:
I now understand how this particular thread got started, and why Gil started it with the example he did. Obviously Karl, and probably yourself, were arguing with Gil on an earlier thread about the implications for “nature†that Avida has now demonstrated (conceding for the moment that Avida has built an IC structure.)
Actually, it got started in a very different way. Go back to Gil’s entry of Sep 28 to see the gory details. Avida didn’t enter seriously into the conversation on that thread or the first 50 comments on this one.
That’s actually pretty sad, because upon rereading Gil’s blog entry, it actually makes more sense when applied to Avida and its ilk than anything else. Tom, Kurt, and someone else jumped on Gil for making a broad statement about simulation that was just silly, and Gil eventually stated that his initial blog entry on that thread should have been taken as sarcasm.
That is sad, because applied to Avida, there is a certain sense talking about mutating the CPU instructions – it is the kind of meta-GA speculation (use a GA to tune the GA parameters!) that occasionally pops up. If that had been Gil’s point, and if it had been clearly stated, we could have avoided this thread entirely!
I personally try to steer clear of most Avida discussion. My knowledge of its workings are extremely rudimentary. I think a lot of A-Life work is still at the digital antfarm level and it is way too easy to take results from Avida (in evolution) or Sugarscape (in social theory) and make broad generalizations from them.
It’s nothing short of hilarious that KeithS and others at ATBC that have obviously not done a single bit of gate level hardware design in their lives are talking about how simulations of gate logic intended to verify a design prior to laying copper need only be modeled with boolean logic. The poor ignoramuses know nothing about analog considerations such as supply rail loading, bus loading, propagation delays, and race conditions just to name a few show stoppers that aren’t covered in simple boolean logic.
In a demonstration of either total cluelessness or dishonesty, in all the commenters there, not a single one has stepped up to correct them. Surely Wesley or someone there knows enough about digital hardware design to tell them there’s a lot more to it than boolean algebra. That’s called a lie of omission. Shame on them.
>>Pav: “my suspicion is that when the first models don’t produce this IC, that some tweaking takes place…. â€Â
>>Reciprocating Bill: “Just so we are clear: You just made all that up.”
Qualifying it as a suspicion implies it is something he doesn’t know to be true.
And just so we are clear, that’s the last bit of stupidity you’re going to be posting here. Hasta la vista, baby.
Who is left?
“Who is left,” you asked John?
Dave Scott, of course. And you. And if I post any more stories that contradict the “big bang”, and upset Mr. Scott, I’ll be gone too. Probably he’s programming the server as I type. Then you’re next, John.
Well, without us both for comic relief, I think U.D. will stand for “Uncommonly Dull”!
“Dog varieties” — John, have you read Sheldrake on poodles? Really?
Of course, the question is this verifiable? And before you scoff, Dr. Dembski himself views consciousness as a potentially external phenomenon.
http://www.sheldrake.org/Artic.....intro.html
Bill wrote, and that’s why I think Shakespeare wise in this well worn quote from Hamlet:
http://www.designinference.com.....chines.htm
PaV: “I now understand how this particular thread got started, and why Gil started it with the example he did.”
Bingo. PaV figured it out.
ROFLMAO!
KeithS responds (paraphrased):
“I knew all along about analog issues. No really, I DID!”
And he still insists I said microprocessors are modeled at the transistor level when I clearly said gate level. Tom English and Karl Pfluger made up that straw man about transistor level.
This is basically why KeithS is no longer here. He’s a lying sack without a clue.
Oh Goody! Now 2ndClass wants to be the next clown I knock down. These people have not done any hardware design. They have not drawn schematics for many complex digital designs then sat thousands of hours in the drivers’s seat of a logic analyzer and oscilloscope debugging their own designs. That and programming is all I did for almost 25 years and I was really, really good at it.
2ndclass sticks his foot in his mouth thusly:
But this article in EDN says:
What a dope. There’s much more at the EDN link.
[(Clown's) coat on in readiness]
I was just looking over the thread, you had previously written:
I can find earlier references to aircraft and biology by you, but I can’t find the example you had previously given about microprocessors (So don’t know if you mentioned transistors, gates, neither or both). Should I suspect foul play here?
I’m not convinced that Tom was putting words in your mouth. You said evolution simulations should work down at the level of protein folding and, AIUI, he says (in 37) that that would be like modelling computers at the level of transistors. He was, I believe, using a simile in fitting with your
primary area of expertise. He didn’t say that you said “computers are modelled at the level of transistors” (or should be). Another generous interprestion was that he was using a BarryAesque “rhetorical flourish”, but I’d go with the first explanation.
After Tom said modeling at the level of proteins and/or transistors is inappropriate, you told him “Your ignorance is showing again” (77) and posted a link and an extract from a page which basically said “IC’s contain a lot of gates and it costs a lot to verify them”. — that in no way contradicted what he had said or implied that he was showing ignorance.
I think at this point, we bad guys assumed that you hadn’t read or understood what you had copied, and were just telling him that he was wrong: i.e transistors are the right level of granularity. Perhaps some one should have asked to elaborate a little.
The next link you gave (in 143) said that existing tools model at the gate level, but that new models allow entire IC’s to be modelled at the transistor level (http://www.techonline.com/comm.....icle/21478)
You quoted a different part from the above, but I think it’s as (or more) relevant. It’s difficult for me to judge what point you were trying to make though, given the past history of this thread.
But this article in EDN says:
AFAICT, those simulations are still using boolean logic but allowing for the fact that gates don’t switch instantly. Karl Plfuger mentioned the timing aspects ages ago. They are not analog simulations (using variable voltages). They mostly seem to allow inputs and outputs to be in one of two states. However there’s a short mention of a new three-state model which uses true,false, and unknown for dealing with cases where input pulses are short compared to the switching time).
It’s not completely clear cut though – one of the graphs, #6, shows something which reminds me of a transistor load graph (or whatever), but I must admit I wasn’t really playing attention on the day we did those at college. My knowledge of transistors really ended at some water operated sluice gate metaphor from a junior electronics kit)
KeithS continues the uncorroborated handwaving. I provide a links from sources like Electronic Design News and IEEE Proceedings that corroborate what I say and the ATBC clowns, in the true way of Darwinian chance worshippers, provide nothing but just-so stories. Color me unimpressed. The bottom line STILL remains that electronic designs are simulated as required at any level right down to the quantum scale while such simulation is quite impossible for biological systems because we don’t know how to model one of the most critical aspects of biological systems – predicting how an arbitrary string of amino acids will fold into the characteristic, unique, and oh-so-important 3D shape of the protein. Just as in simulating electronic designs doesn’t have to ALWAYS be done at such a basic level it’s extremely important that it CAN be done at that basic level.
SteveS
Electronic logic gates don’t change states instantaneously. The length of time it takes them to transition is an analog quantity called propagation delay. The actual delay is effected by many factors including bus loading, temperature, supply voltage, RC time constants of transmission paths, and manufacturing variances. Any simulation that incorporates propagation delay is not strictly boolean anymore. In order to successfully predict what any given arrangment of logic gates will do the prop delays must be accounted for. Often this is done by using synchronous designs and making the clock cycle time generous enough to encompass all conceivable delays. In many situations this is either impossible or impractical. Asynchronous inputs may be unavoidably present and/or clock cycle time made to safely work with the least common denominator is competitively or otherwise impractical.
2ndclass continues his uncorroborated enlightenment as well…
2ndclass – as I’ve already stated, maybe it was too subtle for you, modern microprocessors use mosfets to construct gates. Moreover, the mosfets only operate in two states, on or off. Unlike older silicon transistors, mosfets require no resistive or capacitive elements. Thus instead of modeling a mosfet like a transistor capable of biased operation through a wide range of input/output voltages the mosfet can be treated like a simple on/off switch. As also stated, logic gates made of these basic components require 2 mosfets for an invertor and 4 for a nand gate. All other logic elements can be constructed of nand gates.
I had assumed that I was talking with people who were sufficiently knowledgable to recognize that the difference between modeling a CMOS processor at the transistor level and the gate level is a quibble because the individual logic gates are composed of just a few simple on/off mosfet (transistor) switches.